Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/Silicon Labs/EFR32MG24A120F1536GM48/DCDC_NS/STATUS#0x0
DCDC Status Register
Bypass Switch is currently enabled
DCDC Warmup Done
DCDC is running
VREGIN comparator status
Bypass Comparator Output
DCDC in PFMX mode
https://github.com/cmsis-svd/cmsis-svd-data